1. Field of the Invention
The present invention relates to a thin film transistor (hereinafter, simply referred to as a "TFT") suitable for use in an active matrix type liquid crystal display device (hereinafter, simply referred to as an "AMLCD"), an image sensor or the like, and a method for producing the same.
2. Description of the Related Art
Recently, a liquid crystal display has been receiving much attention as a flat panel display. Specifically, AMLCDs have been incorporated in televisions, projectors, notebook personal computers and the like due to their excellent display quality. In such an AMLCD, amorphous silicon (a-Si) TFTs are used as switching elements for pixels.
However, since the field effect mobility of the a-Si TFT is as low as about 1 cm.sup.2 /V.multidot.s, the a-Si TFT is not usable to form a driving circuit. Therefore, it is necessary to mount, by employing a TAB (Tape Automated Bonding) technique or the like, integrated circuits as drivers along a periphery of a substrate where the switching transistors are formed to produce a display section.
On the other hand, the field effect mobility of a TFT made of polycrystalline silicon (poly-Si) can be as high as 100 cm.sup.2 /V.multidot.s or higher. Thus, the poly-Si TFT can be used to form a driving circuit that can be formed on the same substrate with the switching transistors. In particular, a TFT made of a low-temperature poly-Si, which can be fabricated through a process conducted at a temperature of 600.degree. C. or lower, has been undergoing vigorous studies due to the fact that it can be formed on an inexpensive glass with a lower strain point.
Problems of the poly-Si TFT remaining to be solved include reduction in an off-current (i.e., a leakage current flowing between a source region and a drain region while the transistor is turned off) and enhancement of the current driving ability. In order to solve the above-mentioned problems, a thinner poly-Si film has been considered. A thinner poly-Si film allows an increase in the sheet resistance, thereby reducing the off-current. Moreover, the thinner poly-Si film allows complete depletion of the poly-Si film while the transistor is turned on, thereby reducing a threshold voltage V.sub.TH and enhancing the current driving ability.
However, the thinner poly-Si film increases the resistance of source/drain regions as well. Accordingly, the above-mentioned effect of enhancement in the current driving ability is contradicted. For example, a poly-Si film having an impurity concentration of about 10.sup.20 cm.sup.-3 has a sheet resistance of about several hundred .OMEGA./.quadrature. when the thickness thereof is 100 nm, and a sheet resistance of about several k.OMEGA./.quadrature. when the thickness thereof is 10 nm. Upon simulation, in the case where a TFT has a ratio of a channel length L and a channel width W (L/W) of about 10 .mu.m/10 .mu.m, the resistance of source/drain regions is preferably several hundred .OMEGA. or lower considering the high-speed operation required in a driving circuit. If the channel length of the TFT is shortened in order to realize further enhanced high-speed operation, it is necessary to further reduce the resistance of the source/drain regions. Accordingly, a TFT made of a thinner poly-Si film is not preferable because of deterioration in the current driving ability.
In order to solve the above-described problem, a TFT 400 shown in FIG. 4 has been proposed in which the source/drain regions are made relatively thick while a channel region is made relatively thin (Japanese Laid-Open Patent Publication Nos. 6-163899 and 6-163900).
The TFT 400 shown in FIG. 4 includes a poly-Si film 402 having a channel region and source/drain regions formed on a glass substrate 401, a gate insulating film 403 formed on the poly-Si film 402 and a gate electrode 404 formed on the gate insulating film 403. The TFT is characterized in that the thickness of the poly-Si film 402 is greater in the source/drain regions than in the channel region. In other words, the channel region is thinner than the source/drain regions.
The above-described structure is covered with an interlayer insulating film 405. Source/drain electrodes 406 are formed on the interlayer insulating film 405 so as to be electrically connected to the source/drain regions, respectively, via contact holes provided through the interlayer insulating film 405.
In such a conventional TFT, the step of forming the gate electrode 404 comes after the step of making the source/drain regions thick or the step of making the channel region thin. Accordingly, the relative location of the gate electrode 404 may be greatly offset depending on the accuracy of mask alignment for forming the gate electrode 404. Therefore, conventionally, it is difficult to form a TFT having dimensions in precise accordance with the design and with satisfactory reproducibility.
In the case where a glass substrate is used instead of a quartz substrate, it is difficult to form a plurality of TFTs on a large substrate with accuracy due to problems such as that the substrate may contract in size upon heating during the production process. In order to prevent variation in the transistor characteristics or malfunction in the transistor caused by the dislocation of the gate electrode, the gate electrode needs to be located on the channel region without fail, taking in consideration the process margins such as the accuracy of mask alignment. In order to do so, the plane area of the relatively thin channel region needs to be made large. As shown in FIG. 4, the relatively thin portion of the poly-Si film 402 (i.e., a thin film region) is formed so as to have a size sufficiently greater than the width of the gate electrode 404 along the channel length.
However, in such a structure, the entire area of the thin film region is not used as the channel region and the marginal portions are used as parts of the source/drain regions. Referring to FIG. 4, portions 407a and 407b of the thin film region are shown as the parts of the source/drain regions.
In such a structure, the sheet resistance (series resistance) of the source/drain regions is increased. In the case of a large substrate (e.g., 300 mm.times.400 mm), the process margin is about 2 to 4 .mu.m. Accordingly, when L/W of the TFT is about 10 .mu.m/10 .mu.m, resistance increased due to the process margin is approximately 1 k.OMEGA. which is substantial.
As for the switching transistors, the resistance of the source/drain regions causes little problem, and it is rather important to reduce the off-current.
The off-current cannot be sufficiently reduced only by making the poly-Si film thinner. Accordingly, it has been considered to provide a structure having a substantially undoped region (i.e., an offset structure) or a structure having a lightly doped region (i.e., an LDD structure) between the gate electrode and the source/drain regions. Moreover, semiconductor regions with a bandgap larger than that of other semiconductor regions may be provided between the gate electrode and the source/drain regions.
An undoped region or a lightly doped region formed between the gate and the drain allows reduction in the off-current by easing the electric field concentration at the end of the drain. A semiconductor having a larger bandgap is effective in reducing the off-current due to its smaller carrier density at thermal equilibrium which results in high resistance.
Usually, the offset structure or the LDD structure is formed during the step of implanting ions for forming the source/drain regions, by masking portions to be the offset regions or the LDD regions with a resist. In order to locate semiconductor regions with a larger bandgap at prescribed regions, first, a semiconductor layer with a larger bandgap is deposited and then unnecessary portions of the semiconductor layer are selectively etched away.
The offset or LDD regions are formed (in vertical direction) from a semiconductor layer having a wide bandgap. For a TFT for switching a pixel, it is more important to lay stress on obtaining a lower off-current, whereas, for a TFT used for a driver, it is more important to lay stress on obtaining a higher on-current to enhance the driving ability thereof. Thus, in the case of using the TFT for a driver, it is preferable not to form the offset or LDD regions. It is, however, possible to form the offset or LDD layers when it is desired to improve the reliability of the TFT.
The offset regions, the LDD regions or the semiconductor regions with the larger bandgap are formed in a symmetrical manner with respect to the gate electrode. Otherwise, the on-current will be asymmetric with respect to positive and negative charges of a source-drain voltage, thereby causing problems such as variations in writing signals.